A flash-type EEPROM contains a multiplicity of memory transistors. FIG. 16 shows a schematic sectional view of one of these memory transistors. A memory transistor 200 comprises a source region 55 and a drain region 56, which are impurity diffusion layers formed in a semiconductor substrate 50, and a tunnel oxide film 51, a floating gate 52, a dielectric layer 53, and a control gate 54 which are layered on the semiconductor substrate 50. On the side areas of the layered floating gate 52, dielectric layer 53 and control gate 54, there is provided a side wall 57 made of an insulating material.
In the memory transistor 200, information is programmed by injecting electrons 58 into the floating gate 52 (which is a write operation, indicated by an arrow 59 in FIG. 16) and by drawing the electrons from the floating gate 52 (which is an erase operation, indicated by an arrow 59' in FIG. 16).
In the flash-type EEPROM, an erase operation is performed on a plurality of memory transistors entirely. In most cases, erasure is carried out on the entire EEPROM or on each page corresponding to a group of plural memory transistors. For example, an erase operation is accomplished as described below.
A source voltage Vs, which is a high potential (e.g., 12 V), is applied to the source region 55. At this step, the control gate 54 and the semiconductor substrate 50 have a ground potential, and the drain region 56 is open. In this state, electrons 58 stored in the floating gate 52 are drawn into the source region 55 through the thin tunnel oxide film 51 by means of the Fowler-Nordheim tunnel, as indicated by the arrow 59' in FIG. 16. This results in a threshold voltage Vg of the memory transistor 200 being equal to a threshold voltage level of a common MOS transistor.
In the flash-type EEPROM used as a storage device, it is desirable that the erase operation mentioned above should be carried out at higher speed. Namely, a period of time required for a flash erase operation (i.e., an erase characteristic) is of critical importance in the flash-type EEPROM.
Further, the erase characteristic is required to be uniform among respective memory elements. If the erase characteristic is not uniform among the memory elements, a malfunction may occur in the memory element to cause various problems as mentioned below.
For instance, when the time required for erasure in some memory transistors is longer than a predetermined erase operation time, electrons remain stored in the floating gates of these memory transistors. This condition is called "under-erasure". On the contrary, when the time required for erasure in some memory transistors is shorter than a predetermined erase operation time, electrons are drawn excessively from the floating gates of these memory transistors. This condition is called "over-erasure".
In the case where the degree of variation in the erase characteristic is small among the memory transistors, it is possible to select an erase operation time "T" that allows proper erasure of any memory transistors. However, in case that the degree of variation in the erase characteristic is large, there is a substantial possibility that under-erasure or over-erasure may occur at some cells. Further, in the case where the degree of variation in the erase characteristic is extremely large, under-erasure or over-erasure will occur inevitably in some memory transistors, no matter what erase operation time "T" maybe selected. Thus, it becomes impossible to perform proper erasure in any memory transistors.
For realizing a high-speed flash-type EEPROM, it is required to decrease the erase operation time "T" insofar as possible. Since erasure is performed by drawing electrons from the floating gate 52 to the source region 55 as described above, a higher-speed erase operation may be achieved by increasing an overlapping area of the floating gate 52 and the source region 55. When the overlapping area is too large, however, a problem such as a malfunction may be prone to occur.
Therefore, for a realization of the high-speed flash-type EEPROM, it is required to increase the overlapping area of the source region and floating gate to the extent that no malfunction will occur, while minimizing the degree of variation in the overlapping area among respective memory transistors.